Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

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http://eprints.org/relation/isVersionOf https://researchdata.gla.ac.uk/id/document/1129 http://eprints.org/relation/isVolatileVersionOf https://researchdata.gla.ac.uk/id/document/1129 http://eprints.org/relation/isIndexCodesVersionOf https://researchdata.gla.ac.uk/id/document/1129 archive 6975 disk0/00/00/03/88 2017-02-06 09:05:29 2025-05-21 14:50:58 2017-02-09 16:18:09 data_collection show Georgiev Vihar 14821 0000-0001-6473-2508 Mirza Muhammad M A 34226 0000-0002-1789-224X Dochioiu Alexandru-Iustin 38125 Lema Fikru-Adamu Amoroso Slavatore 17381 Synopsys, Glasgow Towie Ewan 4733 Synopsys, Glasgow Riddet Craig 3543 Synopsys, Glasgow MacLaren Donald 3817 0000-0003-0641-686X Asenov Asen 2244 Paul Douglas 3873 0000-0001-7402-8530 glaresearchdata:2017-02-06-388 Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels pub 30300000 30600000 Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories. 2017-02-06 published University of Glasgow 10.5525/gla.researchdata.388 Image Spreadsheet Text University of Glasgow 69430 1 Engineering Quantum Technology Systems on a Silicon Platform Douglas Paul Engineering & Physical Sciences Research Council (EPSRC) EP/N003225/1 ENG - ENGINEERING ELECTRONICS & NANO ENG 70370 1 SUPERAID7 Asen Asenov European Commission (EC) 688101 ENG - ENGINEERING ELECTRONICS & NANO ENG FALSE English http://ieeexplore.ieee.org/document/7777084/ article 2027-02-09 R FALSE FALSE Experimental and Simulation Study of a High Current 1D Silicon Nanowire Transistor Using Heavily Doped Channels http://eprints.gla.ac.uk/id/eprint/132820