Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

Georgiev, V. and Mirza, M. and Dochioiu, A.-I. and Lema, F.-A. and Amoroso, S. M. and Tow, E. and Riddet, C. and MacLaren, D. A. and Asenov, A. and Paul, D. J. (2017) Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels. [Data Collection]

Enlighten Publications URI: http://eprints.gla.ac.uk/id/eprint/132820

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Silicon nanowires have numerous potential applications, including transistors, memories, photovoltaics, biosensors and qubits [1]. Fabricating a nanowire with the required characteristics for a specific application, however, poses some challenges. For example, a major challenge is that, as the transistors dimensions are reduced, it is difficult to maintain a low off-current (Ioff) whilst simultaneously maintaining a high on-current (Ion). Some sources of this parasitic leakage current include quantum mechanical tunnelling, short channel effects and statistical variability [2, 3]. A variety of new architectures, including ultra-thin silicon-on-insulator (SOI), double gate, FinFETs, tri-gate, junctionless and gate all-around (GAA) nanowire transistors, have therefore been developed to improve the electrostatic control of the conducting channel. This is essential since a low Ioff implies low static power dissipation and it will therefore improve power management in the multi-billion transistors circuits employed globally in microprocessors, sensors and memories.

College / School: College of Science and Engineering > School of Engineering
College of Science and Engineering > School of Physics and Astronomy
Date Deposited: 06 Feb 2017 09:05
Retention date: 9 February 2027
Funder's Name: Engineering & Physical Sciences Research Council (EPSRC), European Commission (EC)
URI: http://researchdata.gla.ac.uk/id/eprint/388

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Georgiev, V. and Mirza, M. and Dochioiu, A.-I. and Lema, F.-A. and Amoroso, S. M. and Tow, E. and Riddet, C. and MacLaren, D. A. and Asenov, A. and Paul, D. J. (2017); Experimental and simulation study of 1D silicon nanowire transistors using heavily doped channels

University of Glasgow

10.5525/gla.researchdata.388

Retrieved: 2017-11-19

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